With the increasing complexity of hardware systems, it is necessary, in order to verify systems or integrated circuits under design, to be able to handle configurations that increasingly include models written in a hardware description language, for example of the HDL type (such as VHDL or Verilog, the most widely used), and in a high level languages of the HLL type (such as C or C++); these languages describe, on the one hand, the elements constituting the hardware, and on the other hand, the models constituting the simulation environment.
The term “Configuration” will be used to refer to a set of software models of elements called “Components,” constituting a global simulation model.
The invention can be used to verify the design of ASICS by simulating their operation, for example in an environment identical or very similar to their end use, the configuration method making it possible to choose components and their software models from a plurality of available models in order to create simulation configurations. In the prior art, the configurations are rigid, and traditionally prepared “by hand” using text editors or graphics editors, based on a predefined list of possible configurations. Each modification in the model in HDL language requires manual corrections to be incorporated into all of the configurations. This happens several times during the development of an ASIC and constitutes a source of errors and modification problems, resulting in production delays. Modifications of a configuration are often sources of errors that are hard to find, as the size of some configurations can reach tens of thousands of lines, making them difficult to handle manually.
The time required to write and debug a configuration can be very long, making it difficult to generate and add new configurations into the environment. For that reason, when an environment contains a lot of elements for which it is difficult to predict all of the usable configurations, the use of certain configuration variants that facilitate debugging (simplified target configurations, for example) is often avoided.
These problems are accentuated in the more and more widely used co-simulation environments, wherein the models come from different sources and are written in high level programming languages (HLL) such as C or C++, or in hardware description languages (HDL) such as VERILOG or VHDL. For the same component of the configuration, there are often several models (ex: functional, in high level programming languages; behavioral, in HDL, synthesizable HDL, etc.) that it would be desirable to be able to use transparently, as needed.
Moreover, the models to be connected often have, at the level of the connecting interfaces, differences requiring the use of adaptation modules. This is the case, for example, for circuits with sophisticated input/output interfaces for which the logical level of the protocol is simulated first, the physical level being developed near the end of the project. The ability to choose adaptation models for the variants of HDL interfaces corresponding to the various development phases of the project constitutes an additional degree of freedom that complicates the writing of the configurations even more. Another problem stems from the fact that mixed HDL (for example Verilog or VHDL)/HLL (for example C++) type models developed separately must be updated coherently. In the case of nonautomated management, this is a potential source of errors.
One object of the present invention is to limit one or more of these drawbacks.